Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

Effects of elevated temperature on tunable near-zero threshold CMOS

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture

Compiler-directed instruction cache leakage optimization

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture

A compiler approach for reducing data cache energy

ICS '03 Proceedings of the 17th annual international conference on Supercomputing

Reducing instruction cache energy consumption using a compiler-based strategy

ACM Transactions on Architecture and Code Optimization (TACO)

Coupling compiler-enabled and conventional memory accessing for energy efficiency

ACM Transactions on Computer Systems (TOCS)

Optimizing Array-Intensive Applications for On-Chip Multiprocessors

IEEE Transactions on Parallel and Distributed Systems

A low power CMOS circuit with Variable Souce Scheme (VSCMOS)

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Reducing dynamic and leakage energy in VLIW architectures

ACM Transactions on Embedded Computing Systems (TECS)