Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS

Authors:
Vjekoslav Svilan;Masataka Matsui;James B. Burr
Affiliations:
Dept. Electrical Engineering, Stanford University, 350 Serra Mall, Stanford, CA;System ULSI Engineering Lab, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki, 210-8520, Japan;Sun Microsystems Laboratories, 2600 Casey Avenue, Bldg. 29, Mountain View, CA
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

An 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35&mgr;m,Vth=0.5 V CMOS process and in a 0.35&mgr;m, back-bias tunable, near-zero Vth process. While standard CMOS atVdd=3.3 V runs at 136 MHz, the same performance can be achieved in the low- Vth version at Vdd=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-Vth version is able to run at 188 MHz, which is 38% faster than standard CMOS.