Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in strong inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation resuits show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.