RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
PLAs in Quantum-dot Cellular Automata
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Defects and faults in QCA-based PLAs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Defect tolerance in QCA-based PLAs
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Design and comparison of NML systolic architectures
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
System-level energy and performance projections for nanomagnet-based logic
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
PLAs in Quantum-Dot Cellular Automata
IEEE Transactions on Nanotechnology
Switching Energy of Ferromagnetic Logic Bits
IEEE Transactions on Nanotechnology
On-Chip Clocking for Nanomagnet Logic Devices
IEEE Transactions on Nanotechnology
Magnetic–Electrical Interface for Nanomagnet Logic
IEEE Transactions on Nanotechnology
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In order to continue the performance and scaling trends that we have come to expect from Moore’s Law, many emergent computational models, devices, and technologies are actively being studied to either replace or augment CMOS technology. Nanomagnet Logic (NML) is one such alternative. NML operates at room temperature, it has the potential for low power consumption, and it is CMOS compatible. In this aricle, we present an NML programmable logic array (PLA) based on a previously proposed reprogrammable quantum-dot cellular automata PLA design. We also discuss the fabrication and simulation validation of the circuit structures unique to the NML PLA, present area, energy, and delay estimates for the NML PLA, compare the area of NML PLAs to other reprogrammable nanotechnologies, and analyze how architectural-level redundancy will affect performance and defect tolerance in NML PLAs. We will use results from this study to shape a concluding discussion about, which architectures appear to be most suitable for NML.