Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A (Sub)Graph Isomorphism Algorithm for Matching Large Graphs
IEEE Transactions on Pattern Analysis and Machine Intelligence
Modeling QCA Defects at Molecular-level in Combinational Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
PLAs in Quantum-dot Cellular Automata
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Proceedings of the 43rd annual Design Automation Conference
Using CAD to shape experiments in molecular QCA
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Molecular QCA design with chemically reasonable constraints
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On the evaluation of scaling of QCA devices in the presence of defects at manufacturing
IEEE Transactions on Nanotechnology
Defect-tolerant adder circuits with nanoscale crossbars
IEEE Transactions on Nanotechnology
A Reconfigurable PLA Architecture for Nanomagnet Logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.00 |
Defect tolerance will be critical in any system with nanoscale feature sizes. This article examines some fundamental aspects of defect tolerance for a reconfigurable system based on Quantum-dot Cellular Automata (QCA). We analyze a novel, QCA-based, Programmable Logic Array (PLA) structure, develop an implementation independent fault model, and discuss how expected defects and faults might affect yield. Within this context, we introduce techniques for mapping Boolean logic functions to a defective QCA-based PLA. Simulation results show that our new mapping techniques can achieve higher yields than existing techniques.