High-speed systolic architectures for finite field inversion

Authors:
Z. Yan;D. V. Sarwate;Z. Liu
Affiliations:
Department of Electrical and Computer Engineering, Lehigh University, 19 Memorial Drive West, Bethlehem, PA 18015, USA;Department of Electrical and Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL 61801-2307, USA;Department of Electrical and Computer Engineering, Lehigh University, 19 Memorial Drive West, Bethlehem, PA 18015, USA
Venue:
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Year:
2005

Citing 7
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New Systolic Architectures for Inversion and Division in GF(2^m)

IEEE Transactions on Computers
High-speed systolic architectures for finite field inversion and division

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Why Systolic Architectures?

Computer
Systolic VLSI Arrays for Polynomial GCD Computation

IEEE Transactions on Computers

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Abstract

Using a new reformulation of the extended Euclidean algorithm, we propose new two-dimensional systolic architectures for inversion in GF(2^m). Our new architectures require considerably less hardware in comparison to the architectures we proposed recently, while achieving the same critical path delays, latencies, and throughputs. Our new architectures compare even more favorably to the inversion architectures proposed previously by others. In common with much previous work in this area, one of our new architectures uses a centralized control mechanism. The other new architecture proposed in this paper uses a distributed control mechanism which results in all the cells in our architecture having the same circuitry regardless of the value of m. Hence the latter new architecture has excellent scalability properties.