High-speed systolic architectures for finite field inversion and division

Authors:
Zhiyuan Yan;Dilip V. Sarwate
Affiliations:
Lehigh University, Bethlehem, PA;University of Illinois at Urbana-Champaign, Urbana, IL
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

Citing 2
Cited 5

New Systolic Architectures for Inversion and Division in GF(2^m)

IEEE Transactions on Computers
High-speed systolic architectures for finite field inversion

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

New Systolic Architectures for Inversion and Division in GF(2^m)

IEEE Transactions on Computers
Area-efficient two-dimensional architectures for finite field inversion and division

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
High-speed systolic architectures for finite field inversion

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398]

Integration, the VLSI Journal
High-speed systolic architectures for finite field inversion

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

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Abstract

Based on a new reformulation of the extended Euclidean algorithm, systolic architectures suitable for VLSI implementations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m2) area-time complexity, O(m) latency, and critical path delays of two logic gates. These architectures show improved performances when compared with previously proposed architectures.