New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
High-speed systolic architectures for finite field inversion and division
Proceedings of the 14th ACM Great Lakes symposium on VLSI
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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The architecture with distributed control described in this paper does not work as claimed. The correct details are provided in this note.