VLSI array processors
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
High-speed systolic architectures for finite field inversion and division
Proceedings of the 14th ACM Great Lakes symposium on VLSI
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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Many high-throughput two-dimensional architectures for finite field inversion and division are based on reformulations of the extended Euclidean algorithm (EEA). These reformulated EEAs usually keep track of two pairs of data polynomials (or registers), and the operations of the reformulated EEAs are only within each pair of polynomials. In this paper, we propose a new reformulated EEA wherein the operations within the two pairs of polynomials are identical. Hence, the two pairs of polynomials in our new reformulated EEA can be concatenated into one pair. By utilizing some inherent properties of the EEA, we further reduce the computational complexity of our reformulated EEA by 25%. Based on our reformulated EEA, we propose new two-dimensional inversion and division architectures. How much hardware saving the reduced computational complexity translates into depends on how control mechanisms are implemented. Regardless of the implementation of control signals, our new architectures require smaller numbers of gates and latches while achieving comparable or better throughput, latency, and critical path delay in comparison to the best architectures in the literature.