Systolic VLSI Arrays for Polynomial GCD Computation

Authors:
Richard P. Brent;H. T. Kung
Affiliations:
Centre for Mathematical Analysis, The Australian National University, Canberra, Australia.;Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA 15213.
Venue:
IEEE Transactions on Computers
Year:
1984

Citing 4
Cited 3

The Design and Analysis of Computer Algorithms

The Design and Analysis of Computer Algorithms
Architecture of the PSC-a programmable systolic chip

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Use of VLSI in algebraic computation: Some suggestions

SYMSAC '81 Proceedings of the fourth ACM symposium on Symbolic and algebraic computation
Why Systolic Architectures?

Computer

High-speed systolic architectures for finite field inversion

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Systolic designs for Aitken's root finding method

Parallel Computing
Improving modular inversion in RNS using the plus-minus method

CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems

Quantified Score

Hi-index	14.98

Visualization

Abstract

The problem of finding a greatest common divisor (GCD) of any two nonzero polynomials is fundamental to algebraic and symbolic computations, as well as to the decoder implementation for a variety of error-correcting codes. This paper describes new systolic arrays that can lead to efricient VLSI solutions to both the GCD problem and the extended GCD problem.