Systematic design approaches for algorithmically specified systolic arrays
Computer architecture
Automating the design of systolic arrays
Integration, the VLSI Journal
Partitioned Matrix Algorithms for VLSI Arithmetic Systems
IEEE Transactions on Computers
Computer
Systolic VLSI Arrays for Polynomial GCD Computation
IEEE Transactions on Computers
Systolic rank updating and the solution of non-linear equations
IPPS '91 Proceedings of the Fifth International Parallel Processing Symposium
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1-D and 2-D systolic arrays for computing the roots of a transcendental function via table generating methods are considered. In particular we show how to derive systolic arrays systematically for a problem with an unbounded computation domain. A non-linear scheduling function is introduced to partition the domain into finite-sized blocks and normal synthesis techniques used to derive block arrays. A m x n block can be computed in at most 3n + m - 1 steps using O(n) cells in a 1-D array and O(mn + n^2) cells in a 2-D array. Different problem instances can be pipelined in the latter and the whole table can be produced by using the arrays iteratively.