A novel arithmetic unit over GF(2m) for low cost cryptographic applications

Authors:
Chang Hoon Kim;Chun Pyo Hong;Soonhak Kwon
Affiliations:
Dept. of Computer and Information Engineering, Daegu University, Jinryang, Kyungsan, Korea;Dept. of Computer and Communication Engineering, Daegu University, Jinryang, Kyungsan, Korea;Dept. of Mathematics and Institute of Basic Science, Sungkyunkwan University, Suwon, Korea
Venue:
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
Year:
2005

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Abstract

We present a novel VLSI architecture for division and multiplication in GF(2m), aimed at applications in low cost elliptic curve cryptographic processors. A compact and fast arithmetic unit (AU) was designed which uses substructure sharing between a modified version of the binary extended greatest common divisor (GCD) and the most significant bit first (MSB-first) multiplication algorithms. This AU produces division results at a rate of one per 2m–1 clock cycles and multiplication results at a rate of one per m clock cycles. Analysis shows that the computational delay time of the proposed architecture for division is significantly less than previously proposed bit-serial dividers and has the advantage of reduced chip area requirements. Furthermore, since this novel architecture does not restrict the choice of irreducible polynomials and has the features of regularity and modularity, it provides a high degree of flexibility and scalability with respect to the field size m.