Matching parallel algorithms with architectures: A case study
Proceedings of the IFIP WG 10.3 working conference on highly parallel computers for numerical and signal processing applications on Highly parallel computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
A Systolic Array Implementation of the Feng-Rao Algorithm
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
High-Speed hardware implementation of rainbow signature on FPGAs
PQCrypto'11 Proceedings of the 4th international conference on Post-Quantum Cryptography
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A systolic architecture is proposed for the triangularization by means of the Gaussian elimination algorithm of large dense n*n matrices over GF(p), where p is a prime number. The solution of large dense linear systems over GF(p) is the major computational step in various algorithms issuing from arithmetic number theory and computer algebra. The proposed architecture implements the elimination with partial pivoting, although the operation of the array remains purely systolic. Extension of the array to the complete solution of a linear system Ax=b over GF(p) is also considered.