VLSI array processors
Systolic Gaussian Elimination Over GF(p) with Partial Pivoting
IEEE Transactions on Computers
A Systolic Array Parallelizing Compiler
A Systolic Array Parallelizing Compiler
Geometric approach to higher weights
IEEE Transactions on Information Theory - Part 1
On the decoding of algebraic-geometric codes
IEEE Transactions on Information Theory - Part 1
IEEE Transactions on Information Theory - Part 1
Fast generalized minimum-distance decoding of algebraic-geometry and Reed-Solomon codes
IEEE Transactions on Information Theory
A Fast Decoding Method of AG Codes from Miura-Kamiya Curves Cab up to Half the Feng-Rao Bound
Finite Fields and Their Applications
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An efficient implementation of a parallel version of the Feng-Rao algorithm on a one-dimensional systolic array is presented in this paper by adopting an extended syndrome matrix. Syndromes of the same order, lying on a slant diagonal in the extended syndrome matrix, are scheduled to be examined by a series of cells simultaneously and, therefore, a high degree of concurrency of the Feng-Rao algorithm can be achieved. The time complexity of the proposed architecture is $m+g+1$ by using a series of $t+\lfloor {\frac{g-1}{2}} \rfloor +1$, nonhomogeneous but regular, effective processors, called PE cells, and $g$ trivial processors, called D cells, where $t$ is designed as the half of the Feng-Rao bound. Each D cell contains only delay units, while each PE cell contains one finite-field inverter and, except the first one, one or more finite-field multipliers. Cell functions of each PE cell are basically the same and the overall control circuit of the proposed array is quite simple. The proposed architecture requires, in total, $t+\lfloor {\frac{g-1}{2}} \rfloor +1$ finite-field inverters and ${\frac{(t+\lfloor (g-1)/2 \rfloor)(t+\lfloor (g-1)/2 \rfloor +1)}{2}}$ finite-field multipliers. For a practical design, this hardware complexity is acceptable.