Low-complexity bit-parallel multiplier over GF(2m) using dual basis representation

Authors:
Chiou-Yng Lee;Jenn-Shyong Horng;I-Chang Jou
Affiliations:
Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taoyuan County;Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung;Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung
Venue:
Journal of Computer Science and Technology
Year:
2006

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Abstract

Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF(2m) using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented. The architecture is optimized in order to minimize the silicon covered area (transistor count). The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF(2m).