A dual basis bit-serial systolic multiplier for GF(2m)

Authors:
S. T. J. Fenn;D. Taylor;M. Benaissa
Affiliations:
-;-;-
Venue:
Integration, the VLSI Journal
Year:
1995

Citing 0
Cited 2

Test generation in systolic architecture for multiplication over GF(2m)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architecture for bit parallel systolic multipliers for special class of GF(2m) using dual bases

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test

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Abstract