VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardware-efficient programmable FIR processor using input-data and tap folding
EURASIP Journal on Applied Signal Processing
Implementation and analysis of stream ciphers based on the elliptic curves
Computers and Electrical Engineering
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A low-complexity VLSI array of versatile multiplier in normal basis over GF(2n) is presented. The finite field parameters can be changed according to the user's requirement and make the multiplier reusable in different applications. It increases the flexibility to use the same multiplier for different applications and reduces the user's cost. The proposed multiplier has a regular structure and is very suitable for high speed VLSI implementation. In addition, the pipeline versatile multiplier can be modified to a low-cost architecture which is feasible in embedded systems and restricted computing environments.