Parallel implementation of Cholesky LLT-algorithm in FPGA-based processor

Authors:
Oleg Maslennikow;Volodymyr Lepekha;Anatoli Sergiyenko;Adam Tomas;Roman Wyrzykowski
Affiliations:
Technical University of Koszalin, Koszalin, Poland;National Technical University of Ukraine, Kiev, Ukraine;National Technical University of Ukraine, Kiev, Ukraine;Czestochowa University of Technology, Czestochowa, Poland;Czestochowa University of Technology, Czestochowa, Poland
Venue:
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
Year:
2007

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Abstract

The fixed-size processor array architecture, which is intended for realization of matrix LLT-decomposition based on Cholesky algorithm, is proposed. In order to implement this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. The AU is intended for configuring in the Xilinx Virtex4 FPGAs, and its hardware complexity is much less than the complexity of similar AUs operating with floating-point numbers.