BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
Partitioning Hardware and Software for Reconfigurable Supercomputing Applications: A Case Study
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Optimized high-order finite difference wave equations modeling on reconfigurable computing platform
Microprocessors & Microsystems
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
C is for circuits: capturing FPGA circuits as sequential code for portability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A case study of hardware/software partitioning of traffic simulation on the Cray XD1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA-based, floating-point reduction operations
MATH'06 Proceedings of the 10th WSEAS International Conference on APPLIED MATHEMATICS
High-performance computing with desktop workstations
MATH'06 Proceedings of the 10th WSEAS International Conference on APPLIED MATHEMATICS
Parallel implementation of Cholesky LLT-algorithm in FPGA-based processor
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM SIGARCH Computer Architecture News
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Solving diffractive optics problems using graphics processing units
Optical Memory and Neural Networks
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In order to take advantage of the significant benefits afforded by computational electromagnetic techniques, such as the Finite-Difference Time-Domain (FDTD) method, solvers capable of analyzing realistic problems in a reasonable time frame are required. Although software-based solvers are frequently used, they are often too slow to be of practical use. To speed up computations, hardware-based implementations of the FDTD method have been recently proposed. In this paper, we present our most recent progress in the area of FPGA-based 3D FDTD accelerators. Three aspects of the design are discussed, including the host-PC interface, memory hierarchy, and computational datapath. Implementation and benchmarking results are also presented, demonstrating that this accelerator is capable of at least three-fold speedups over thirty-node PC clusters.