An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster
Cluster Computing
64-bit floating-point FPGA matrix multiplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Parameterized floating-point logarithm and exponential functions for FPGAs
Microprocessors & Microsystems
Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
High-throughput bayesian computing machine with reconfigurable hardware
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Parallel implementation of Cholesky LLT-algorithm in FPGA-based processor
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Rapid development of high performance floating-point pipelines for scientific simulation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.