A Novel Cotransformation for LNS Subtraction
Journal of Signal Processing Systems
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A RISC architecture for 2DLNS-based signal processing
International Journal of High Performance Systems Architecture
| Hi-index | 14.98 |
In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realised? Herein we describe the European Logarithmic Microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful; that for 32-bit work logarithmic arithmetic may now be the technique of choice.