Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Numerical methods for computer science, engineering, and mathematics
Numerical methods for computer science, engineering, and mathematics
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Representations of Discrete Functions
Representations of Discrete Functions
A History of Computing Technology, 2nd Edition
A History of Computing Technology, 2nd Edition
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
High-Performance Architectures for Elementary Function Generation
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
A method to decompose multiple-output logic functions
Proceedings of the 41st annual Design Automation Conference
High-Speed Function Approximation Using a Minimax Quadratic Interpolator
IEEE Transactions on Computers
A New Range-Reduction Algorithm
IEEE Transactions on Computers
Table-based polynomials for fast hardware function evaluation
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Optimal Curve Fitting With Piecewise Linear Functions
IEEE Transactions on Computers
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
On the optimization of heterogeneous MDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Numerical function generators (NFGs) realize arithmetic functions, such as ex, sin(πx), and √x, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.