Logarithmic multiplier in hardware implementation of neural networks

Authors:
Uroš Lotrič;Patricio Bulić
Affiliations:
Faculty of Computer and Information Science, University of Ljubljana, Slovenia;Faculty of Computer and Information Science, University of Ljubljana, Slovenia
Venue:
ICANNGA'11 Proceedings of the 10th international conference on Adaptive and natural computing algorithms - Volume Part I
Year:
2011

Citing 5
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Abstract

Neural networks on chip have found some niche areas of applications, ranging from massive consumer products requiring small costs to real-time systems requiring real time response. Speaking about latter, iterative logarithmic multipliers show a great potential in increasing performance of the hardware neural networks. By relatively reducing the size of the multiplication circuit, the concurrency and consequently the speed of the model can be greatly improved. The proposed hardware implementation of the multilayer perceptron with on chip learning ability confirms the potential of the concept. The experiments performed on a Proben1 benchmark dataset show that the adaptive nature of the proposed neural network model enables the compensation of the errors caused by inexact calculations by simultaneously increasing its performance and reducing power consumption.