Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
IEEE Transactions on Computers
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
ISC '01 Proceedings of the 4th International Conference on Information Security
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
A Novel Pipelined Threads Architecture for AES Encryption Algorithm
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Memories: A Survey of Their Secure Uses in Smart Cards
SISW '03 Proceedings of the Second IEEE International Security in Storage Workshop
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
A high-throughput low-cost AES processor
IEEE Communications Magazine
Hardware-software co-design of AES on FPGA
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As networking technology advances, the gap between network bandwidth and network processing power widens. Information security issues add to the need for developing high-performance network processing hardware, particularly that for real-time processing of cryptographic algorithms. This paper presents a configurable architecture for Advanced Encryption Standard (AES) encryption, whose major building blocks are a group of AES processors. Each AES processor provides 219 block cipher schemes with a novel on-the-fly key expansion design for the original AES algorithm and an extended AES algorithm. In this multicore architecture, the memory controller of each AES processor is designed for the maximum overlapping between data transfer and encryption, reducing interrupt handling load of the host processor. This design can be applied to high-speed systems since its independent data paths greatly reduces the input/output bandwidth problem. A test chip has been fabricated for the AES architecture, using a standard 0.25-µm CMOS process. It has a silicon area of 6.29 mm2, containing about 200,500 logic gates, and runs at a 66-MHz clock. In electronic codebook (ECB) and cipher-block chaining (CBC) cipher modes, the throughput rates are 844.9, 704, and 603.4 Mb/s for 128-, 192-, and 256-b keys, respectively. In order to achieve 1-Gb/s throughput (including overhead) at the worst case, we design a multicore architecture containing three AES processors with 0.18- m CMOS process. The throughput rate of the architecture is between 1.29 and 3.75 Gb/s at 102 MHz. The architecture performs encryption and decryption of large data with 128-b key in CBC mode using on-the-fly key generation and composite field S-box, making it more cost effective (with better thousand-gate/gigabit-per-second ratio) than conventional methods.