A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
IEEE Transactions on Computers
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
ISC '01 Proceedings of the 4th International Conference on Information Security
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A high-throughput low-cost AES processor
IEEE Communications Magazine
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
A direction to avoid re-encryption in cryptographic file sharing
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to 219 different AES block cipher schemes within a reasonable hardware cost. Data can be encrypted not only with secret keys and initial vectors, but also by different block ciphers during the communication. A novel on-the-fly key expansion design is also proposed for 128-, 192-, and 256-bit keys. Our unified hardware can run both the original AES algorithm and the extended AES algorithm. The proposed processor design has been fabricated by a 0.25μm CMOS process, with a silicon area of 6.93mm2---about 200.5K equivalent gates. Under a 66MHz clock, the throughput rate for both the ECB and CBC operation modes are 844.8Mbps, 704Mbps, and 603.4Mbps for 128-bit, 192-bit, and 256-bit keys, respectively.