An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
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IBM Journal of Research and Development
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A very compact "Perfectly masked" S-box for AES
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
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NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable memory based AES co-processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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IWSEC'06 Proceedings of the 1st international conference on Security
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In this paper, we present a high-speed AES IP-core, which runs at 780 MHz on a 0.13µm CMOS standard cell library, and which achieves 10 Gbps throughput in all encryption modes, including CBC mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining techniques cannot be applied. To reduce the propagation delays of the S-Box, the most critical function block, we developed a special circuit architecture that we call twisted-BDD, where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.