A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Low-power techniques for network security processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design and test of a scalable security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A mesh-structured scalable IPsec processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation and performance evaluation of a high throughput crypto coprocessor
Journal of Parallel and Distributed Computing
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
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We propose an efficient hardware implementation of the advanced encryption standard algorithm, with key expansion capability. Compared to the widely used table lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64 percent. Our pipelined design has a very high throughput rate. Using typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate in the non-feedback cipher mode is 2.38 Gb/s for 128-bit keys, 2.008 Gb/s for 192-bit keys, and 1.74 Gb/s for 256-bit keys, respectively. Testability of the design is also considered. The hardware cost of the AES design is approximately 58 K gates using a standard synthesis flow.