An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A high-throughput low-cost AES processor
IEEE Communications Magazine
A network security processor design based on an integrated SOC design and test platform
Proceedings of the 43rd annual Design Automation Conference
STEAC: a platform for automatic SOC test integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE standard 1500 compatible delay test framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT platform is also implemented for the design-test integration. The security processor has been fabricated with 0.18μm CMOS technology. The core area is 3.899mm x 2.296mm (525K gates approximately) and the operating clock rate is 83MHz.