Area, delay, and power characteristics of standard-cell implementations of the AES s-box

  • Authors:
  • Stefan Tillich;Martin Feldhofer;Johann Großschädl

  • Affiliations:
  • Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria

  • Venue:
  • SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
  • Year:
  • 2006

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Abstract

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, whereby hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examined implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by more than an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.