Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
Computer Organization and Design, Fourth Edition, Fourth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
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In cryptography, the advanced encryption standard (AES) is an encryption standard issued as FIPS by NIST as a successor to data encryption standard (DES) algorithm. The applications of the AES are wide including any sensitive data that requires cryptographic protection before communication or storage. This paper proposes extending general-purpose processors with crypto coprocessor based on decoupled architectures. The extended coprocessor splits an encryption/decryption instruction into memory (load/store) and computation (encryption/decryption) portions (pseudo instructions). Loading/storing and encrypting/decrypting data are performed in parallel and communicated through architectural queues. The computational unit includes parallel AES pipelines for fast encrypting/decrypting data. On four parallel AES pipelines, our results show a performance of 222 Giga bits per second.