An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
IEEE Transactions on Computers
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
On the S-Box Architectures with Concurrent Error Detection for the Advanced Encryption Standard
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers
IEEE Transactions on Computers
Architectures for cryptography accelerators
Architectures for cryptography accelerators
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Double-Data-Rate Computation as a Countermeasure against Fault Analysis
IEEE Transactions on Computers
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Invariance-based concurrent error detection for advanced encryption standard
Proceedings of the 49th Annual Design Automation Conference
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The faults that accidently or maliciously occur in the hardware implementations of the Advanced Encryption Standard (AES) may cause erroneous encrypted/decrypted output. The use of appropriate fault detection schemes for the AES makes it robust to internal defects and fault attacks. In this paper, we present a lightweight concurrent fault detection scheme for the AES. In the proposed approach, the composite field S-box and inverse S-box are divided into blocks and the predicted parities of these blocks are obtained. Through exhaustive searches among all available composite fields, we have found the optimum solutions for the least overhead parity-based fault detection structures. Moreover, through our error injection simulations for one S-box (respectively inverse S-box), we show that the total error coverage of almost 100% for 16 S-boxes (respectively inverse S-boxes) can be achieved. Finally, it is shown that both the application-specific integrated circuit and field-programmable gate-array implementations of the fault detection structures using the obtained optimum composite fields, have better hardware and time complexities compared to their counterparts.