IEEE Transactions on Computers
A cryptography core tolerant to DFA fault attacks
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
Design and characterisation of an AES chip embedding countermeasures
International Journal of Intelligent Engineering Informatics
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Concurrent fault detection for a hardware implementation of the Advanced EncryptionStandard (AES) is important not only to protect the encryption/decryption process fromrandom faults. It will also protect the encryption/decryption circuitry from an attacker whomay maliciously inject faults in order to find the encryption secret key. In this paper wepresent a novel fault detection scheme which is based on a multiple parity bit code and showthat the proposed scheme leads to very efficient and high coverage fault detection. We thenestimate the associated hardware costs and detection latencies.