Area Efficient Exponentiation Using Modular Multiplier/Squarer in GF(2m

Authors:
Hyun-Sung Kim;Kee-Young Yoo
Affiliations:
-;-
Venue:
COCOON '01 Proceedings of the 7th Annual International Conference on Computing and Combinatorics
Year:
2001

Citing 5
Cited 2

Finite field for scientists and engineers

Finite field for scientists and engineers
VLSI array processors

VLSI array processors
Systolic Multipliers for Finite Fields GF(2m)

IEEE Transactions on Computers
The VLSI Implementation of a Reed Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm

IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Bit-Serial AOP Arithmetic Architectures over GF (2m)

InfraSec '02 Proceedings of the International Conference on Infrastructure Security
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a new exponentiation architecture and multiplier/squarer for GF(2m), which uses a standard basis representation. The proposed multiplier/squarer is used as kernel architecture of exponentiation. Although the proposed multiplier/squarer computes the multiplication and squaring operations at the same time in GF(2m), the common parts existing in both operations are only executed once, thereby reducing the required hardware compared to related systolic circuits. The proposed multiplier/squarer can be easily applied to exponentiation architecture. It is also well suited to VLSI implementation because of its regularity, modularity, and unidirectional data flow.