The VLSI Implementation of a Reed Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm

Authors:
In-Shek Hsu;I. S. Reed;T. K. Truong; Ke Wang; Chiunn-Shyong Yeh;L. J. Deutsch
Affiliations:
Department of Electrical Engineering, University of Southern California;-;-;-;-;-
Venue:
IEEE Transactions on Computers
Year:
1984

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Abstract

Berlekamp has developed for the California Institute of Technology Jet Propulsion Laboratory (JPL) a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes, using a dual basis over a Galois field. The conventional RS encoder for long codes often requires lookup tables to perform multiplication of two field elements. Berlekamp's algorithm requires only shifting and EXCLUSIVE OR operations. It is shown in this paper that the new dual-basis (255,223) RS encoder can be realized readily on a single VLSI chip with NMOS technology.