A new modular exponentiation architecture for efficient design of RSA cryptosystem

Authors:
Ming-Der Shieh;Jun-Hong Chen;Hao-Hsuan Wu;Wen-Ching Lin
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

Modular exponentiation with a large modulus, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems for secured data communications. To speed up the computation, the Montgomery modular multiplication algorithm is used to relax the process of quotient determination, and the carry-save addition (CSA) is employed to reduce the critical path delay. In this paper, based on the inherent data dependency between the modular multiplication and square operations in the H-algorithm of modular exponentiation, we present a new modular exponentiation architecture with a unified modular multiplication/square module and show how to reduce the number of input operands for the CSA tree by mathematical manipulation. The developed architecture has the following advantages. 1) There is no need to convert the carry-save form of an operand into its binary representation at the end of each modular multiplication. In this way, except the final step to get the result of modular exponentiation, the time-consuming carry propagation can then be eliminated. 2) The number of input operands for the CSA tree is reduced in a very efficient way. 3) The hardware saving is achieved with very limited impact on the original critical path delay when designed with two distinct modular multiplication and square components. Experimental results show that our modular exponentiation design obtains the least hardware complexity compared with the existing work and outperforms them in terms of area-time (AT) complexity as well.