Bit-level systolic arrays for modular multiplication
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
Modular Reduction in GF(2n) without Pre-computational Phase
WAIFI '08 Proceedings of the 2nd international workshop on Arithmetic of Finite Fields
A new modular exponentiation architecture for efficient design of RSA cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
An efficient implementation of montgomery powering ladder in reconfigurable hardware
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
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Modular multiplication is widely used in cryptographic algorithms. In order to improve the efficiency, most of the recent implementations adopt precomputation. Precomputation improves the speed and in the meanwhile makes the algorithms more complex. The complex algorithms are not suitable for hardware implementation. We propose a new algorithm without precomputation, which is more efficient even compared with the ones with precomputation. Our algorithm is based on interleaving modular algorithm. The modulus in our algorithm is enlarged, and this modification greatly reduces the number of subtractions. By a small change of the multiplier, our algorithm does not need the last subtraction. We also propose a pipeline scheme which can achieve high frequency. Compared with existing work (including the precomputation ones), our implementation improves the throughput/area by 47%.