The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Systolic Modular Multiplication
IEEE Transactions on Computers
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A tamper resistant hardware accelerator for RSA cryptographic applications
Journal of Systems Architecture: the EUROMICRO Journal
Compact modular exponentiation accelerator for modern FPGA devices
Computers and Electrical Engineering
A Hardware Architecture for Integrated-Security Services
Transactions on Computational Science IV
Design and implementation of real time secured RS232 link for multiple FPGA communication
Proceedings of the 2011 International Conference on Communication, Computing & Security
Incorporating error detection in an RSA architecture
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
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In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on large integers, that can be reduced to repeated modular multiplications. We present a serial implementation of RSA, which is based upon an optimized version of the RSA algorithm originally proposed by P.L. Montgomery. The proposed architecture is innovative, and it widely exploits specific capabilities of Xilinx programmable devices. As compared to other solutions in the literature, the proposed implementation of the RSA processor has smaller area occupation and comparable performance. The final performance level is a function of the serialization factor. We provide a thorough discussion of design tradeoffs, in terms of area requirements vs performance, for different values of the key length and of the serialization factor.