Incorporating error detection in an RSA architecture

Authors:
L. Breveglieri;I. Koren;P. Maistri;M. Ravasio
Affiliations:
Department of Electronics and Information Technology, Politecnico di Milano, Milano, Italy;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Department of Electronics and Information Technology, Politecnico di Milano, Milano, Italy;STMicroelectronics, Agrate Brianza, Milano, Italy
Venue:
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Year:
2006

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Abstract

Most successful attacks against hardware implementations of cryptographic systems make use of side-channel information leakage. Recently, some attacks have been proposed against various cryptosystems, which exploit deliberate error injection during the computation process. Several error detection schemes have been proposed in order to counteract these attacks. In this paper, we add a residue-based error detection scheme to an RSA architecture and evaluate the area and latency overheads with respect to the basic architecture.