Compact modular exponentiation accelerator for modern FPGA devices

Authors:
Timo Alho;Panu Hämäläinen;Marko Hännikäinen;Timo D. Hämäläinen
Affiliations:
Nokia Technology Platforms, P.O. Box 68, FI-33721 Tampere, Finland;Nokia Technology Platforms, P.O. Box 68, FI-33721 Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland
Venue:
Computers and Electrical Engineering
Year:
2007

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Abstract

We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of modern FPGAs. The accelerator consumes 434 logic elements, four 9-bit DSP elements, and 13604 memory bits in Altera Stratix EP1S40. It performs modular exponentiations with up to 2250-bit integers and scales easily to larger exponentiations. Excluding pre- and post-processing time, 1024-bit and 2048-bit exponentiations are performed in 26.39ms and 199.11ms, respectively. Due to its compactness, standard interface, and support for different clock domains, the accelerator can effortlessly be integrated into a larger system in the same FPGA. The accelerator and its performance are demonstrated in practice with a fully functional prototype implementation consisting of software and hardware components.