Static resource models for code-size efficient embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dual-pipeline heterogeneous ASIP design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Customization of application specific heterogeneous multi-pipeline processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Optimizing power consumption at high-level is a criticalstep towards power-efficient digital system designs. Thispaper addresses the power management problem byscheduling a given control-dominated data flow graph. Wediscuss delay and power issues with scheduling, andpropose an improvement algorithm for insertion of so-calledsoft edges which enable power optimization undertiming constraints. Power savings obtained by our approachon tested circuits range between 15% and 30% of the initialpower dissipation.