A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Resource constrained dataflow retiming heuristics for VLIW ASIPs
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
PSCP: a scalable parallel ASIP architecture for reactive systems
Proceedings of the conference on Design, automation and test in Europe
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
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In this paper we demonstrate the feasibility of a dual pipeline Application Specific Instruction Set Processor. We take a C program and create a target instruction set by compiling to a basic instruction set, from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL descriptions to construct a dual pipeline processor. Our results show that in comparison to the single pipeline Application Specific Instruction Set Processor, the performance improves by 27.6% and switching activity reduces by 6.1% for a number of benchmarks. These improvements come at the cost of increased area which for benchmarks considered is 16.7% on average.