A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Resource constrained dataflow retiming heuristics for VLIW ASIPs
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
Proceedings of the conference on Design, automation and test in Europe
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Dual-Pipeline Heterogeneous ASIP Design
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
A scalable configurable architecture for the massively parallel GCA model
International Journal of Parallel, Emergent and Distributed Systems - Advances in Parallel and Distributed Computational Models
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In this paper we propose Application Specific Instruction Set Processors with heterogeneous multiple pipelines to efficiently exploit the available parallelism at instruction level. We have developed a design system based on the Thumb processor architecture. Given an application specified in C language, the design system can generate a processor with a number of pipelines specifically suitable to the application, and the parallel code associated with the processor. Each pipeline in such a processor is customized, and implements its own special instruction set so that the instructions can be executed in parallel with low hardware overhead. Our simulations and experiments with a group of benchmarks, largely from Mibench suite, show that on average, 77% performance improvement can be achieved compared to a single pipeline ASIP, with the overheads of 49% on area, 51% on leakage power, 17% on switching activity, and 69% on code size.