The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 15th international symposium on System Synthesis
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
ASIP Design Methodologies: Survey and Issues
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Journal of Signal Processing Systems
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Software-Defined Radio (SDR) provides the flexibility to enable cost-effective multi-mode terminals. However, the growing complexity of the new communication standards, which need to be executed with the reduced energy budget required by battery-powered devices, is still challenging architects. Although Coarse Grain Array (CGA) -based processors extended with domain specific instructions are considered strong candidates to undertake both the high-performance and low power, the lack of efficient methodologies to derive optimal instances of such an architecture paradigm is still a major limitation. In this paper, an extensive energy-performance exploration of a CGA-based SDR processor is presented. This approach targets sufficient relative accuracy on the optimization metrics, which assures meaningful comparisons between different instances, while the absolute accuracy is relaxed and traded off against simulation time. The balance between the different sources of architectural parallelism, such as data and instruction level parallelism is crucial in order to achieve the required performance at minimum energy cost. Accordingly, the proposed method is used to select the optimal DLP---ILP combination required to run the symbol-based baseband processing of a 100 Mbps+ WLAN (Wireless Local Area Network) receiver in a CGA-based processor. As a result, a 4 脳 4 array with four ways SIMD (Single Instruction, Multiple Data) extensions is shown to be the optimal instance, providing minimum energy consumption and real-time processing guarantees.