REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Minimizing register usage penalty at procedure calls
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Minimum cost interprocedural register allocation
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Practical improvements to the construction and destruction of static single assignment form
Software—Practice & Experience
Smallest-last ordering and clustering and graph coloring algorithms
Journal of the ACM (JACM)
Journal of Algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Complexity of Function Pointer May-Alias Analysis
TAPSOFT '97 Proceedings of the 7th International Joint Conference CAAP/FASE on Theory and Practice of Software Development
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Optimal register allocation for SSA-form programs in polynomial time
Information Processing Letters
On the Complexity of Register Coalescing
Proceedings of the International Symposium on Code Generation and Optimization
On the complexity of spill everywhere under SSA form
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A fast cutting-plane algorithm for optimal coalescing
CC'07 Proceedings of the 16th international conference on Compiler construction
Register allocation for programs in SSA-Form
CC'06 Proceedings of the 15th international conference on Compiler Construction
Optimal register sharing for high-level synthesis of SSA form programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect customization for a hardware fabric
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Increasing the Scope and Resolution of Interprocedural Static Single Assignment
SAS '09 Proceedings of the 16th International Symposium on Static Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power, performance and security optimized hardware design for H.264
Proceedings of the Sixth Annual Workshop on Cyber Security and Information Intelligence Research
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is to allocate the minimum number of registers such that no scalar variable is spilled to memory. Previously, an optimal polynomial-time algorithm for this problem has been presented for individual procedures represented in Static Single Assignment (SSA) Form. This result is now extended to complete programs (or sub-programs), as long as: (1) each procedure is represented in SSA Form; and (2) at every procedure call, all live variables are split at the call point. With this representation, it is possible to ensure that the interprocedural interference graph (IIG) is chordal, and can therefore be colored optimally in polynomial time. An optimal coloring of the IIG can be achieved by allocating registers for each procedure individually. Previous work has shown that optimal register allocation in SSA Form does not require an interference graph. Optimal interprocedural register allocation, therefore, is achieved without constructing an interference graph, giving the optimal algorithm a significant runtime advantage over prior sub-optimal heuristics.