The maximum k-colorable subgraph problem for chordal graphs
Information Processing Letters
Quality and speed in linear-scan register allocation
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Fusion-based register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Journal of Algorithms
Optimal spilling for CISC machines with few registers
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Fast copy coalescing and live-range identification
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Node-and edge-deletion NP-complete problems
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Optimized interval splitting in a linear scan register allocator
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
Graphs and Hypergraphs
Tailoring Graph-coloring Register Allocation For Runtime Compilation
Proceedings of the International Symposium on Code Generation and Optimization
Optimal register allocation for SSA-form programs in polynomial time
Information Processing Letters
Optimal bitwise register allocation using integer linear programming
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Register allocation for programs in SSA-Form
CC'06 Proceedings of the 15th international conference on Compiler Construction
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
Progressive spill code placement
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Studying optimal spilling in the light of SSA
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Graph-coloring and treescan register allocation using repairing
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Split register allocation: linear complexity without the performance penalty
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Hi-index | 0.00 |
Compilation for embedded processors can be either aggressive (time consuming cross-compilation) or just in time (embedded and usually dynamic). The heuristics used in dynamic compilation are highly constrained by limited resources, time and memory in particular. Recent results on the SSA form open promising directions for the design of new register allocation heuristics for embedded systems and especially for embedded compilation. In particular, heuristics based on tree scan with two separated phases -- one for spilling, then one for coloring/coalescing -- seem good candidates for designing memory-friendly, fast, and competitive register allocators. Still, also because of the side effect on power consumption, the minimization of loads and stores overhead (spilling problem) is an important issue. This paper provides an exhaustive study of the complexity of the "spill everywhere" problem in the context of the SSA form. Unfortunately, conversely to our initial hopes, many of the questions we raised lead to NP-completeness results. We identify some polynomial cases but that are impractical in JIT context. Nevertheless, they can give hints to simplify formulations for the design of aggressive allocators.