Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Register allocation in the SPUR Lisp compiler
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Lisp on a reduced-instruction-set processor: characterization and optimization
Lisp on a reduced-instruction-set processor: characterization and optimization
Tutorial : reduced instruction set computers
Tutorial : reduced instruction set computers
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Global optimization by suppression of partial redundancies
Communications of the ACM
Reduced register saving/restoring in single-window register files
ACM SIGARCH Computer Architecture News
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
The dream of a lifetime: A lazy variable extent mechanism
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
Processor Design Tradeoffs in VLSI
Processor Design Tradeoffs in VLSI
A portable machine-independent global optimizer--design and measurements
A portable machine-independent global optimizer--design and measurements
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code Optimization Across Procedures
Computer
Inline function expansion for compiling C programs
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation across procedure and module boundaries
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
The effect on RISC performance of register set size and structure versus code generation strategy
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Subprogram Inlining: A Study of its Effects on Program Execution Time
IEEE Transactions on Software Engineering
Unexpected side effects of inline substitution: a case study
ACM Letters on Programming Languages and Systems (LOPLAS)
How to analyze large programs efficiently and informatively
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Processor Architecture and Data Buffering
IEEE Transactions on Computers
Space-efficient closure representations
LFP '94 Proceedings of the 1994 ACM conference on LISP and functional programming
Complexity of bi-directional data flow analysis
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Interprocedural optimization: eliminating unnecessary recompilation
ACM Transactions on Programming Languages and Systems (TOPLAS)
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
A generalized theory of bit vector data flow analysis
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Compiler transformations for high-performance computing
ACM Computing Surveys (CSUR)
Register allocation using lazy saves, eager restores, and greedy shuffling
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Interprocedural register allocation for lazy functional languages
FPCA '95 Proceedings of the seventh international conference on Functional programming languages and computer architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
TIL: a type-directed optimizing compiler for ML
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Hot cold optimization of large Windows/NT applications
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A new algorithm for partial redundancy elimination based on SSA form
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Call-cost directed register allocation
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Partial redundancy elimination in SSA form
ACM Transactions on Programming Languages and Systems (TOPLAS)
Comparative study of page-based and segment-based software DSM through compiler optimization
Proceedings of the 14th international conference on Supercomputing
Efficient and safe-for-space closure conversion
ACM Transactions on Programming Languages and Systems (TOPLAS)
A study of devirtualization techniques for a Java Just-In-Time compiler
OOPSLA '00 Proceedings of the 15th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
OS and compiler considerations in the design of the IA-64 architecture
ACM SIGPLAN Notices
OS and compiler considerations in the design of the IA-64 architecture
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Optimization of available C compilers for the MC68HC11
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Bidirectional data flow analysis: myths and reality
ACM SIGPLAN Notices
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Inter-procedural stacked register allocation for itanium® like architecture
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Evaluation of Compiler-Assisted Software DSM Schemes for a Workstation Cluster
IWIA '99 Proceedings of the 1999 International Workshop on Innovative Architecture
Register allocation by priority-based coloring
ACM SIGPLAN Notices - Best of PLDI 1979-1999
TIL: a type-directed, optimizing compiler for ML
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post Register Allocation Spill Code Optimization
Proceedings of the International Symposium on Code Generation and Optimization
Optimal register reassignment for register stack overflow minimization
ACM Transactions on Architecture and Code Optimization (TACO)
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploitation of multicore systems in a java virtual machine
IBM Journal of Research and Development
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Inter-procedural register allocation can minimize the register usage penalty at procedure calls by reducing the saving and restoring of registers at procedure boundaries. A one-pass inter-procedural register allocation scheme based on processing the procedures in a depth-first traversal of the call graph is presented. This scheme can be overlaid on top of intra-procedural register allocation via a simple extension to the priority-based coloring algorithm. Using two different usage conventions for the registers, the scheme can distribute register saves/restores throughout the call graph even in the presence of recursion, indirect calls or separate compilation. A natural and efficient way to pass parameters emerges from this scheme. A separate technique uses data flow analysis to optimize the placement of the save/restore code for registers within individual procedures. The techniques described have been implemented in a production compiler suite. Measurements of the effects of these techniques on a set of practical programs are presented and the results analysed.