Minimizing register usage penalty at procedure calls
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Designing the TFP Microprocessor
IEEE Micro
Instruction scheduling for the Motorola 88110
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
A technique of global optimization of microprograms
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
A Fine-Grain Parallelizing Compiler
A Fine-Grain Parallelizing Compiler
Code optimization of pipeline constraints
Code optimization of pipeline constraints
Efficient instruction scheduling using finite state automata
Proceedings of the 28th annual international symposium on Microarchitecture
| Hi-index | 0.00 |
The paper presents a technique called Global Instruction Distribution that globally fine-tunes the code produced for a superscalar processor. The fine-tuning is effected by distributing instructions from one block to other blocks according to the control flow graph of the program. The method does not involve instruction scheduling, but models resource usage to find the best insertion points in the target basic block. We present our implementation of GID in a production compiler, and show how the GID framework allows incorporation of additional functions targeting different optimizations. Performance measurements on the MIPS R8000 are presented to demonstrate the practicality and efficacy of this approach.