Reconfigurable parallel inner product processor architectures

Authors:
Rong Lin
Affiliations:
SUNY-Geneseo, Geneseo, NY
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2001

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Abstract

This paper presents a novel approach for low-power high-performance inner product processor design. The processor is dynamically reconfigurable for computing inner products of input arrays with four or more combinations of array dimensions and precision. The processor mainly consists of an array of 8/spl times/8 or 4/spl times/4 small multipliers plus two or three arrays of adders. It requires very simple reconfigurable components. The whole network may be reconfigured by using a few control bits for the desired computations, and the reconfiguration can be done dynamically. The design is regular, modular, and can easily be pipelined, and most parts of the network are symmetric and repeatable. A set of low-power high-performance parallel counters is also proposed for the implementation of the design, which could lead to a significant reduction in worst case power dissipation compared with traditional binary-logic based architectures, while showing superiority in speed, VLSI area, and layout simplicity.