The Design of an Optoelectronic Arithmetic Processor Based on Permutation Networks
IEEE Transactions on Computers
A VLSI inner product macrocell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Reconfigurable parallel inner product processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computers
Computer
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor
Proceedings of the 12th ACM Great Lakes symposium on VLSI
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A run-time reconfigurable array of multipliers architecture
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
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This paper presents a novel unified run-time reconfiguable arithmetic processor design scheme. It provides novel computational trade-offs between array/matrix size and input data item bitwidth, and efficiently performs multiple types of arithmetic operations in pipeline within a single hardware-reusable processor. The proposed computations include inner product evaluation, matrix multiplication, and evaluation of polynomial. More specifically, we show that the minimum hardware platform can be easily reconfigured to compute: (1) the inner products of two input arrays with several combinations of array dimension and precision, including input arrays of 256 4-bit items, 64 8-bit items, 16 16-bit items, 4 32-bit items and 1 64-bit item; (2) the product of matrices Xnk and Ykm for any integers n, k, m and any item precision b ranging from 4 to 64 bits, including input arrays of X16x16 Y16x16 of 4-bit items, X8x8 and Y8x8 of 8-bit items, X4x4, Y4x4 of 16-bit items, X2x2, Y2x2 of 32-bit items and the product of two 64-bit numbers; (3) the polynomial evaluations at any given point x, with several combinations of the polynomial degree N and evaluation point number precision p, including polynomial degree and item precision options of N=64, p=8, N=16, p=16, and N=4, p=32.