A VLSI inner product macrocell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable parallel inner product processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A run-time reconfigurable array of multipliers architecture
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A processor-in-memory architecture for multimedia compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel self-repairable and reconfigurable inner-product processor with low-power, fast CMOS circuits and DFT techniques is presented. It takes the advantage of recently proposed decomposition based arithmetic circuit design approach for simple implementation of the reconfigurations, component replacements, and high-quality tests.The processor can be dynamically reconfigured for two types operations: 4 x 8 x 8-b inner product computation and 16 x 16-b multiplication. The self-repair is provided by choosing a fault-free one from 17 possible architectures during the test, which covers more than 52% transistors for the specified faults. Only one extra bit is needed for all reconfigurations, repairs, and tests. The proposed exhaustive DFT technique greatly reduces the test vector length, from 17*232 to 1.5*213, which is as short as that required by the pseudo-exhaustive DFT method recently reported in literature.